The present invention relates to computer-aided design (CAD) tools for analyzing integrated circuits and, more particularly, to analyzing power Vdd and ground nets in integrated circuits for electromigration, voltage drop and ground bounce.
Aggressive development within the semiconductor industry keeps electronic products moving on a brisk course forward. With each new generation of integrated circuit (IC) chips, device geometries and supply voltages are decreasing while the clock frequencies are increasing. Typical ICs today contain more than three million transistors and include three to five layers of metal interconnects that supply power and transport signals.
Along with smaller device geometries come narrower metal lines and larger resistances. Also, as more devices are interconnected, the lines are getting longer, further increasing the interconnect resistance. The substantial voltage drops that develop across metal power nets cause the circuits to malfunction, especially when the supply voltage is reduced below 3 volts. For example, a 1 volt drop in a 3 volt system would have a much more severe impact on circuit functionality than a proportional drop in a 5 volt system. So, in deep submicrometer designs (feature sizes less than 0.5 .mu.M), voltage drop analysis is crucial. Additionally, the narrower metal lines have undesirable wear-out of metal wiring caused by electromigration.
Ground bounce is due to the inductance in the IC package pins and bonding wires and the current switching (dI/dt) in the integrated circuit. Ground bounce noise may affect circuits in various ways. For example, ground bounce noise may degrade the performance of the circuit. Additionally, ground bounce noise may cause the circuit to malfunction due false latching in receiving chips.
In deep submicron design, the circuit consumes more power which means that dI/dt is even greater than in non-submicron designs. The ground bounce problem in the past was more significant in output buffers than on-chip circuits. However, the ground bounce noise in on-chip circuits is becoming more important with today's technologies.
Numerous CAD tools exist for simulating transistor networks of ICs (e.g., SPICE). An innovative system is described in U.S. patent application Ser. No. 08/040,531, entitled "Transistor-Level Timing and Power Simulator and Power Analyzer", filed Mar. 29, 1993 by Huang et al., and U.S. patent application Ser. No. 08/231,207, entitled "Power Diagnosis for VLSI Designs", filed Apr. 21, 1994 by An-Chang Deng, which are both hereby incorporated by reference for all purposes. However, none of the prior art systems allow the user to simulate the power nets of an IC and display power net characteristics like voltage drop, current density and ground bounce. The present invention fulfills this and other needs.